1. Field of the Invention
The present invention relates to the field of integrated circuit chip testing; more specifically, it relates to a space transformer for use in a system for testing integrated circuit chips on a wafer.
2. Background of the Invention
Typical wafer level test of integrated circuit chips consists of a set of probes for contacting controlled collapse chip connections (C4s also known as solder bumps) and contact pads of the integrated circuit chip mounted to a space transformer which in turn is mounted to a probe card, the probe card is in turn connected to a tester. The tester supplies power, ground and signals to the integrated circuit chip also known as a device under test (DUT). Three basic problems must be overcome when testing semiconductor integrated circuit chips in this manner. First, the amount of power to be supplied must be sufficient to respond to power surges while transistors and other devices in the integrated circuit chip are switching. Second, as power surges occur, coupling noise on signal lines is generated which must be minimized. Third, with high power consumption integrated circuits unwanted heat generation within the space transformer can occur.